As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin-like field effect transistor (FinFET). A typical FinFET is fabricated with a thin “fin” (or fin structure) extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. It is beneficial to have a gate on both sides of the channel allowing gate control of the channel from both sides. Advantages of FinFET devices include reducing the short channel effect and higher current flow.
Because of the complexity inherent in nonplanar devices, such as FinFETs, a number of techniques used in manufacturing planar transistors must be redesigned for manufacturing nonplanar devices. For example, mask overlay and alignment techniques may require further design efforts. ICs (integrated circuits) are typically assembled by layering features on a semiconductor wafer using a set of photolithographic masks. Each mask in the set has a pattern formed by transmissive or reflective regions. During a photolithographic exposure, radiation such as ultraviolet light passes through or reflects off the mask before striking a photoresist coating on the wafer. The mask transfers the pattern onto the photoresist, which is then selectively removed to reveal the pattern. The wafer then undergoes processing steps that take advantage of the shape of the remaining photoresist to create circuit features on the wafer. When the processing steps are complete, photoresist is reapplied and wafer is exposed using the next mask. In this way, the features are layered to produce the final circuit.
Regardless of whether a mask is error-free, if all or part of the mask is not aligned properly, the resulting features may not align correctly with adjoining layers. This can result in reduced device performance or complete device failure. To measure mask alignment, overlay (OVL) marks are formed on the wafer. Overlay marks typically consist of layers of material arranged in patterns that are both recognizable and that provide identifiable reference points. While existing overlay marks have been generally adequate for planar devices, they have not been entirely satisfactory for manufacturing nonplanar devices.